1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a fabricating method thereof, more particularly, to a flash/EEPROM in a semiconductor device and a fabricating method thereof.
2. Background of the Related Art
EEPROM is characterized in two categories: a byte erasure type and a flash type. The flash type is further divided into a hot-electron injection type and a F-N(Fowler-Nordhein) current type. An EEPROM/flash type memory device is basically constructed with a MOS transistor having stacked polysilicon gates including a floating gate and a control gate. When there are no electrons in the floating gate, a channel for current to flow through is generated as voltage is applied to the control gate and the voltage applied to the control gate exceeds a threshold voltage to form the channel. When electrons are accumulated in the floating gate, the voltage applied to the control gate forms the channel at a higher level than when there are no electrons in the floating gate because of an electric field offset effect due to the negative charges in the floating gate.
A semiconductor non-volatile memory operates by the principle that electrons accumulated in the floating gate will be unable to escape when an energy barrier exists in both the silicon substrate and the control gate. Electron injection and discharge are performed on a floating gate of a semiconductor non-volatile memory to make the memory electrically rewritable where the threshold voltage of a memory cell increases proportionally with the amount of injected electrons. A non-volatile memory in a semiconductor device is enabled by designating an electron-accumulated state as xe2x80x981xe2x80x99 and a non-electron state as xe2x80x980xe2x80x99 because electrons accumulated around the floating gate do not escape and external electrons do not enter into the floating gate.
A basic structure of a stacked gate, which introduces no selection gate, is similar to a UV-erasing type memory device and is particularly useful for fabricating a highly-integrated memory device. Erasing is achieved by having a control gate, which is either grounded or receiving a negative voltage, and applying a high voltage to a source, resulting in a F-N current between the source and a floating gate thus decreasing the threshold voltage. Alternatively, a negative voltage may be applied to the substrate for a blanket erasing.
Source/drain regions of a non-volatile memory device such as an EEPROM are impurity diffusion regions doped heavily with impurities, while a channel region is formed in an active area of a substrate over which the floating and control gates overlap each other.
Cell programming is achieved by injecting hot channel electrons, which are generated from a drain stage of the channel region by applying a predetermined voltage to the control gate and the drain region, respectively, into a floating gate. Programming is achieved by hot channel electron injection so that the hot carriers generated near the drain are injected into the floating gate from the drain, provided that the channel region is inversed by applying a high voltage to the control gate and applying a proper voltage to the drain, where the source and well are grounded. Erasing is achieved by discharging carriers stored in the floating gate. Erasing of an EEPROM is completed by U-V erasure or by applying a high voltage to the source or drain regions or the bulk. Reading is achieved by judging a cell status of on/off by means of reading the threshold voltage of a cell transistor. For instance, once the control gate and the drain are supplied with 5V and 1V respectively, the threshold voltage of the programmed cell becomes high (at least over 5V) to be xe2x80x98offxe2x80x99, while the erased cell becomes low to be xe2x80x98onxe2x80x99. In other words, EEPROM (electrically erasable and programmable read only memory) enables data to be programmed and erased electrically, which means that EEPROM installed in a system enables the system to rewrite data with ease.
Flash EEPROM developed from EEPROM enables programming of data by a byte or more according to the design and to erase data by bits or a block, thereby improving the operating speed of EEPROM greatly. Accordingly, a non-volatile flash memory device, of which integration is superior to that of EEPROM, meets the needs of a high capacity memory device and enables high speed data reading operation for portable office automation. However, a flash memory device of 1 Tr type (ETOX) fabricated by the related art consumes electric current excessively, thereby requiring an oversized voltage pump circuit. And, the flash memory device according to the related art requires an additional circuit for preventing electrical disturbance if a selection gate is not introduced. Moreover, the more frequently the device is used, the less reliable the flash memory device according to the related art becomes because of the limited endurance of programming and erasing.
FIG. 1A and FIG. 1B show cross-sectional views seen from the directions of channel length and width, respectively, of an EEPROM device in a semiconductor device fabricated by a related art. In FIGS. 1A-1B, a field oxide layer 11 defining a device isolation area and a device active area are formed by LOCOS (local oxidation of silicon) on predetermined portions of a silicon substrate 10, thereby exposing the device active area. In the active area of the substrate 10, a gate insulating layer 12 formed of oxide, a floating gate 13 formed of polysilicon on the gate insulating layer 12, an inter-poly layer 14 formed of an insulator of an O-N-O structure, and a control gate 15 of polysilicon are formed.
A method of fabricating a non-volatile memory device according to the related art includes forming a second conductive type well in a predetermined portion of a first conductive type silicon substrate 10, then forming by LOCOS a field oxide layer 11, which acts as a device isolation layer. Next, a gate oxide layer 12 is formed by oxidizing a surface of the substrate 10 thermally and a polysilicon layer is deposited on the gate oxide layer 12, followed by the formations of a floating gate 13 by patterning the polysilicon layer and the gate insulating layer so that the polysilicon layer and the gate insulating layer remain within a memory cell only. An O-N-O layer 14 is then formed on an exposed top surface of the floating gate 13.
After an upper polysilicon layer has been deposited on the substrate including the surface of the O-N-O layer 14, where the O-N-O layer 14 acts as an insulating layer between the polysilicon layers, a control gate 15 is formed in a direction along the length of the channel by patterning the upper polysilicon layer to extend to another memory cell. Then, an impurity diffusion region 16 is formed by implanting first conductive type impurity ions, where the control gate 15 is used as a mask, then diffusing the impurity ions to form source and drain regions 16. In this case, the impurity diffusion regions 16 may be formed with either a symmetrical junction or an asymmetrical junction, where the symmetrical junction is used for a negative erase while the asymmetrical junction used for a positive erase.
As mentioned in the above description of the non-volatile memory device (of a single poly gate type EEPROM) fabricated by the related art, the area occupied by a cell with a single gate is relatively large and the voltage applied for programming and erasing operations carried out by F-N tunneling is relatively high. Moreover, in a split gate type EEPROM constructed with 2 or 3 gates according to the related art, programming and erasing are achieved by the injection of hot electrons and by F-N tunneling, respectively. Namely, the split gate type introduces a structure where the control gate covers the floating gate.
As described above, the related art EEPROM have various disadvantages. The split-gate type EEPROM according to the related art produces disturbances and consumes lots of power when a programming is carried out by hot electron injection. Additionally, in a non-volatile memory cell according to the related art, it is difficult to increase a coupling ratio, which is defined as the areas of the control gate and the floating gate in contact with the inter-poly layer 14 where the coupling ratio depends on a planar structure that does not include the part over the field oxide layer 11.
An object of the present invention is directed to a non-volatile semiconductor memory device and a fabricating method thereof that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a flash/EEPROM in a semiconductor device and a fabricating method thereof that prevents programming disturbance and enables programming operated by a byte unit by achieving a programming and an erasing of a memory device through a F-N tunneling using a coupling ratio between floating and control gates.
Another object of the present invention is to provide a flash/EEPROM in a semiconductor device and a fabricating method thereof that has a floating gate over a control gate having a source region less overlapped than a drain region.
Another object of the present invention is to provide a flash/EEPROM in a semiconductor device and a fabricating method thereof that reduces a cell area by removing a control transistor.
Another object of the present invention is to provide a flash/EEPROM in a semiconductor device and a fabricating method thereof that prevents programming disturbance and enables programming operated by a byte unit by achieving a programming and an erasing of a memory device through a F-N tunneling using a coupling ratio between floating and control gates by means of forming a structure where the control gate is covered with the floating gate, a drain region is properly overlapped by coupling, and a source region is less overlapped.
Another object of the present invention is to provide a memory device compatible with a flash EEPROM by realizing various functions such as MCU on one chip.
Another object of the present invention is to realize an ultra-highly integrated device by reducing a cell area itself and a total memory area by means of removing a control transistor for erasing by byte unit in an EEPROM.
To achieve at least these and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes a control gate on a semiconductor substrate in which a device active area and a device isolation are defined, the control gate lying on the device active area, the control gate dividing the device active area into a first region and a second region wherein a control gate insulating layer is inserted between the substrate and the control gate, a first insulating layer covering a top surface and a side of the control gate, a drain junction in the first region of the substrate, a source junction in the second region, the source junction separated from the control gate to a predetermined distance, a second insulating layer on the second region between the source junction and the control gate and on a predetermined portion of a surface of the first region between the first insulating layer and the drain junction, and a floating gate covering the second insulating layer and the first insulating layer.
To further achieve the above objects in a whole or in part, a non-volatile semiconductor memory device according to the present invention can further include a third insulating layer at a later surface of the first insulating layer, an insulating interlayer covering the device active area including a surface of the floating gate, a contact hole in a predetermined portion of the insulating interlayer, the contact hole exposing a portion of the drain junction in the first region where the floating gate is not located, and a bit line on the insulating interlayer, the bit line contacted with the drain junction through the contact hole.
To further achieve the above objects in a whole or in part, a semiconductor device according to the present invention includes a plurality of device active areas separated from one another in parallel by a plurality of device isolation layers in a first direction on a semiconductor substrate where a plurality of memory cell areas are defined, a plurality of control gates crossing over the device active areas and the device isolation layers, where the respective control gates are separated from one another in a second direction perpendicular to the first direction, a plurality of drain junctions in the device active areas at one side of the respective control gates, respectively, a plurality of source junctions in the device active areas at the other side of the respective control gates, respectively, the respective source junctions are separated from the control gates by a predetermined distance, respectively, and a plurality of floating gates overlap with the control gates, portions of the drain junctions, and portions of the device active areas where the source junctions are not formed at the other sides of the control gates, respectively.
To further achieve the above objects in a whole or in part, the lay out of the semiconductor device according to the present invention can further include a plurality of bit line contacts at predetermined portions of the drain junctions which are not overlapped with the floating gates in the memory cell areas, respectively, and a plurality of bit lines contacted with the respective bit line contacts, the bit lines overlapped with the respective device active areas, the bit lines extending to the first direction.
To further achieve the above objects in a whole or in part, a method of forming a semiconductor device according to the present invention includes forming a control gate on a predetermined portion of a memory cell area of a semiconductor substrate wherein the memory cell area which is divided into a first region and a second region by the control gate is defined by a device isolation layer and wherein a control gate insulating layer is inserted between the control gate and the semiconductor substrate, forming a first insulating layer on an exposed surface of the control gate, forming a drain junction in the first region, forming a third insulating layer covering predetermined portions of the second region and the drain junction wherein the third insulating layer is extended from the first insulating layer, forming a floating gate on the third insulating layer and an exposed surface of the first insulating layer, and forming a source junction in the second region which is not overlapped with the floating gate.
To further achieve the above objects in a whole or in part, after the step of forming the first insulating layer, the method can further include forming a second insulating layer on a surface of the first insulating layer at a side of the control gate wherein the second insulating layer differs from the first insulating layer greatly in etch selectivity.
To further achieve the above objects in a whole or in part, the forming a third insulating layer and a floating gate can include forming an oxide layer on the exposed surface of the first region and a tunneling oxide layer on the second region of the substrate, forming a conductive layer over the substrate including the oxide layer, the tunneling oxide layer, and the first insulating layer, and patterning the conductive layer, the oxide layer and the tunneling oxide layer to be overlapped with the control gate and portions of the drain and source junctions.
To further achieve the above objects in a whole or in part, a method of forming a semiconductor device according to the present invention includes the steps of forming a control gate on a predetermined portion of a memory cell area of a semiconductor substrate wherein the memory cell area which is divided into a first region and a second region by the control gate is defined by a device isolation layer and wherein a control gate insulating layer is inserted between the control gate and the semiconductor substrate, forming a first insulating layer on an exposed surface of the control gate, forming a second insulating layer on a surface of the first insulating layer at a side of the control gate wherein the second insulating layer differs from the first insulating layer greatly in etch selectivity, forming a drain junction in the first region, forming an oxide layer on the exposed surface of the first region and a tunneling oxide layer on the second region of the substrate, forming a conductive layer over the substrate including the oxide layer, the tunneling oxide layer, and the first insulating layer, forming a floating gate and a third insulating layer by patterning the conductive layer, the oxide layer and the tunneling oxide layer to be overlapped with the control gate and portions of the drain and source junctions, and forming a source junction in the second region which is not overlapped with the floating gate.
To further achieve the above objects in a whole or in part, after the forming the source junction in the second region, the method can further include forming an insulating layer over the semiconductor substrate including the floating gate, forming a contact hole exposing a portion of the drain junction which is not covered with the floating gate by removing a portion of the insulating layer, and forming a bit line on the insulating interlayer wherein the bit line fills up the contact hole.
To further achieve the above objects in a whole or in part, in a non-volatile semiconductor memory device including a plurality of memory cells each of which consists of a control gate, a drain junction, a source junction, a floating gate, a word line, and a bit line, wherein an electric charge Q1 of a first parasitic capacitor generated from a voltage Vcg applied to the control gate and a voltage Vfg induced on the floating gate is C1 (Vcgxe2x88x92Vfg) and C1 is a capacitance of the first parasitic capacitor, wherein an electric charge Q3 of a third parasitic capacitor generated from a voltage Vs at the source junction and a voltage Vfg induced on the floating gate is C3(Vsxe2x88x92Vfg) and C3 is a capacitance of the third parasitic capacitor, wherein an electric charge Q4 of a fourth parasitic capacitor generated from a voltage Vb at a bulk and a voltage Vfg induced on the floating gate is C4(Vbxe2x88x92Vfg) and C4 is a capacitance of the fourth parasitic capacitor, and wherein an electric charge Q2 of a second parasitic capacitor generated from a voltage Vd at the drain junction and a voltage Vfg induced on the floating gate is C2(Vdxe2x88x92Vfg) and C2 is a capacitance of the second parasitic capacitor, to further achieve the above objects in a whole or in part, a method of preventing disturbance of a non-volatile semiconductor memory according to the present invention includes such that (1) a programming is achieved by selecting one of two variables Vcg and Vd which prevents the disturbance at the word line and the bit line according to the formula Vfg=(C1Vcg+C2Vd)/Ctotal and wherein the programming is achieved by F-N tunneling using voltage difference between the floating gate and the source junction and a channel region at a side of the source junction, thereby injecting electrons into the floating gate, and (2) an erasing is achieved by discharging electrons accumulated in the floating gate in use of F-N tunneling, which uses voltage difference between the floating gate and a lateral side of the source junction, and wherein the erasing is achieved by selecting the voltages Vcg and Vs not to discharge the electrons into the source junction due to a voltage applied to another memory cells sharing the word line. Preferably, Vfg is equal to [C1Vcg+C2Vd+C3Vs+C4Vb]/Ctotal as total of the electric charges (Q1+Q2+Q3+Q4) of the first to fourth parasitic capacitors is approximately equal to 0 when the floating gate at neutral and Ctotal is approximately equal to C1+C2+C3+C4.